1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a synchronous semiconductor memory device which is synchronized with an external, periodically applied clock signal to receive an external signal. More specifically, the present invention relates to a randomly accessible, synchronous dynamic random access memory (SDRAM).
2. Description of the Background Art
While dynamic random access memories (DRAMs) used as main memory have been accessed more and more rapidly, their operating speeds still cannot catch up with those of microprocessors (MPUs). It is thus often said that the access time and cycle time of DRAM are the bottleneck, which degrades the entire performance of systems. In recent years SDRAMs which operate synchronously with a clock signal have been manufactured as main memories for high-speed MPUs.
An SDRAM achieves rapid access by synchronizing with a system clock signal to rapidly access successive bits, e.g., eight bits for each of data input/output terminals. For example, 8-bit data can be successively read in an SDRAM capable of inputting and outputting data of eight bits (one byte) through data input/output terminals DQ0-DQ7. In other words, data of eight bits multiplied by eight, i.e., data of 64 bits can be read successively.
The number of bits of successively read or written data is referred as burst length, which can be changed by mode register in SDRAM.
In an SDRAM, external control signals, i.e., a row address strobe signal ext./RAS, a column address strobe signal ext./CAS, a column address strobe signal ext./CAS, an address signal Add and the like are received at a rising edge of an external clock signal Ext.CLK as a system clock, for example.
FIG. 16 is a schematic block diagram showing a configuration of an internal clock generation circuit 2000 which receives external clock signal Ext.CLK and converts it into an internal clock signal int.CLK in a conventional synchronous dynamic random access memory.
Internal clock generation circuit 2000 includes a clock input terminal 2002 which receives external clock signal Ext.CLK, an NAND circuit 2004 which receives Ext.CLK from clock input terminal 2002 at one input node and a ground potential GND at the other input node, an inverter 2006 which receives an output from NAND circuit 2004, and a clock buffer circuit 2008 which receives an output from inverter 2006 to generate an internal clock signal int.CLK with a predetermined pulse width.
For the configuration of the conventional internal clock generation circuit 2000, when an SDRAM is in standby state, external clock signal Ext.CLK is constantly input to clock buffer 2008. Thus, even when the SDRAM in standby state, clock buffer 2008 is constantly in operating state, which results in significant electricity consumption. Thus, the electricity consumption of the SDRAM in standby state cannot be reduced.
Meanwhile, a method of reducing electricity consumption in a state other than the power-down mode, e.g., standby state, in an SDRAM has been proposed, for example, in Japanese Patent Laying-Open No. 7-177015. According to this technique, a power cutting circuit is provided for an external input/output pin of an SDRAM and the power for the input first-stage circuit of the external input/output pin is cut in standby state to reduce electricity consumption. However, the technique relates to cutting the power for the input initial-stage circuit of the external input/output pin and is not pertinent to a problem to be solved by the present invention, i.e., the reduction of the electricity consumption of the internal clock generation circuit for more rapidly accessed SDRAMs.
Furthermore, Japanese Patent Laying-Open No. 7-182857 has suggested a method of reducing electricity consumption by allowing refreshing a DRAM which operates according to a clock in a microcomputer system without generating a clock signal in standby state. However, this technique is not pertinent to the internal clock generation circuit which converts an external clock signal into an internal clock signal in an SDRAM as an application of the present invention, and does not contemplate the reduction of the electricity consumption of the internal clock generation circuit for more rapidly accessed SDRAMs.
FIG. 17 is a schematic block diagram showing a configuration of an internal clock generation circuit 3000 with an improved configuration of the conventional internal clock generation circuit 2000 shown in FIG. 16.
Internal clock generation circuit 3000 includes clock input terminal 2002 which receives external clock signal Ext.CLK, an NAND circuit 3004 which is connected to clock input terminal 2002 at one input node and also receives a ground potential at the other input node, an inverter 3006 which receives an output of NAND circuit 3004, a first clock buffer circuit 3008 which receives an output from inverter 3006 to output a first internal clock signal int.CLK-A, and a second clock buffer circuit 3010 which is controlled by a signal .phi..sub.ACT for designating activating an operation of an internal circuit to provide a memory cell selecting operation in response to external control signals, and receives the output from inverter 3006 and outputs a second internal clock signal int.CLK-B.
More specifically, while signal .phi..sub.ACT attains inactive low level, the conventional internal clock generation circuit 3000 stops the operation for outputting the second internal clock signal int.CLK-B. By contrast, the first internal clock signal int.CLK-A is constantly generated and external control signals which provide a command for executing the next operation is responsively received.
Thus, while the first internal clock signal int.CLK-A is required to constantly operate to receive a command for specifying the next operation, the second internal clock signal int.CLK-B for controlling the other internal circuit operations is generated after signal .phi..sub.ACT is activated.
That is, when an SDRAM is in standby state and signal .phi..sub.ACT is inactivated (i.e., at low level), the operation of the second clock buffer 3010 is stopped and thus electricity consumption can be reduced in standby state.
However, the conventional internal clock generation circuit 3000 also requires the first clock buffer circuit 3008 to constantly operate, and sufficient reduction in electricity consumption cannot be achieved in standby state. In addition, the electricity consumption in the clock buffer circuit in standby state is increased as clock frequency is increased, i.e., as the SDRAM is operated more rapidly, and thus it is more difficult for an SDRAM with higher performance to suppress electricity consumption.